FIG. 1 is a simplified plan view of a prior art interline charge-coupled device (CCD) image sensor. Image sensor 100 includes photodetectors 102 arranged in rows and columns to form an imaging area 104. A vertical CCD (VCCD) shift register 106 is disposed between the columns of photodetectors 102. Charge packets 108 accumulate in the photodetectors 102 in response to incident light. The charge packets are transferred to respective shift register elements 110 in VCCD shift registers 106 and shifted one row at a time to horizontal CCD (HCCD) shift register 112. For simplicity, only one column of charge packets 108 is depicted in FIG. 1. Once in the HCCD shift register 112, the charge packets 108 are serially shifted through HCCD shift register 112 to output circuit 114.
FIG. 2 is a cross-sectional view of VCCD shift register 106 along line A-A shown in FIG. 1. VCCD shift register 106 is depicted as a two-phase CCD, where two distinct gate electrodes 200, 202 are associated with each row of photodetectors. The first gate electrode 200 is clocked with signal V1 and the second gate electrode 202 with signal V2.
VCCD shift register 106 is built on an n-type substrate 204 with a p-type layer 206 disposed between substrate 204 and n-type buried channel 208. The clock signals V1 and V2 alter the potential energy within buried channel 208 to control the shifting of charge packets through the VCCD shift register 106. With an n-type buried channel, the majority charge carriers are electrons that form the charge packets and flow in the n-type buried channel 208. Holes, the minority charge carrier, will flow in the p-type layer 206.
As discussed earlier, the charge packets shifted through buried channel 208 are generated by photons (i.e., light). In an interline CCD image sensor, photons can also produce undesirable electrons known as dark current in the VCCD shift registers. Accumulation mode clocking can be used to reduce the amount of dark current generated in the VCCDs. Accumulation mode clocking maintains all of the gate electrodes 200, 202 at a negative voltage with respect to substrate 204 prior to transferring charge packets from the photodetectors to the VCCD shift registers. This causes holes to accumulate at the surface of the buried channel 208 under the gate electrodes 200, 202. The abundance of holes at the surface suppresses the generation of dark current. Charge packets are then transferred to the VCCD shift registers and gate electrodes 200 and 202 alternately clocked at higher voltage levels to shift the charge packets through the VCCD shift registers 106. The alternating clocking patterns repeat until all of the charge packets have been shifted through the VCCD shift registers 106. A description of the benefits of accumulation mode clocking of CCD's may be found in U.S. Pat. No. 4,963,952 and in the book entitled “Solid-State Imaging with Charge-Coupled Devices” by Albert J. P. Theuwissen.
Because p-type layer 206 is a thin layer confined between substrate 204 and n-type buried channel 208, p-type layer 206 cannot easily act as a source or sink of holes. So when gate electrodes 200, 202 are clocked into accumulation mode, holes flow from well contact 210 at the perimeter of the vertical CCD shift registers through p-type layer 202. The distances the holes must travel from well contact 210 can be long, and p-type layer 202 has a high resistance to the flow of holes.
FIG. 3 illustrates an equivalent circuit of VCCD shift registers across a row in an interline CCD image sensor. The nth gate electrode (gate electrode n) has a capacitance to p-type layer 206 given by C. P-type layer 206 has a resistance from well contact 210 to the nth gate electrode given by (n×R). When the nth gate electrode is clocked into accumulation or depletion, the amount of time it takes for holes to flow from well contact 210 is related to the product of (n×R)×(n×C)=n2×RC. For large area CCD image sensors, this amount of time is too long and reduces the advantage of accumulation mode clocking.
Additionally, when only one clock signal, such as V1, has a rising edge from a low voltage (e.g., −9 V) to a higher voltage (e.g., 0 V), the voltage on the resistors will not stay at ground (GND). Instead, the voltage on the resistors will “bounce” positive with the V1 clock edge and slowly return back to ground. This ground bounce produces poor charge shifting through the VCCD shift registers.
U.S. Pat. Nos. 6,586,784 and 6,995,795 address the problem of ground bounce by implementing the timing pattern shown in FIG. 4 for accumulation mode clocking. The clock signals V1 and V2 are clocked to three different voltage levels, a negative −15 volts (V), a negative −9 V, and zero V. During time T0, both the V1 and V2 clock signals are set at −9 V allowing holes to accumulate at the surface of the buried channel. At the transition from time T0 to time T1, the V2 clock signal has a negative going voltage transition 400 to compensate the positive going transition 402 on the V1 clock signal. These compensated voltage transitions can prevent ground bounce by causing no net flow of holes through the p-type layer (e.g. layer 206). This solution, however, can have a serious problem. The −15 V on the clock signals is very negative and can significantly reduce the lifetime of the gate oxides. The −15 V can also cause charge injection through the gate oxide directly into the CCD channel.